I have verified the power up sequence as outlined in the NVIDIA Jetson TX2 OEM Product Design Guide but I do not get any serial port traffic from UART0. Our carrier board receives the CARRIER_PWR_ON signal and powers everything up and releases RESET_OUT#, but I don’t see anything happen after that. The TX2 module works great on the developer kit carrier board…
What can I check to see why I don’t see any serial port data?
Thank you!
Hi kpaulsen,
Had you referred to Tegra Linux Driver Package TX2 Adaptation Guide already?
You could also check [Release 28.2 Development Guide]-> [U-Boot Customization]-> [TX2 Configuring Pinmux GPIO and PAD]
Please review the schematic and also the pinmux spreadsheet settings to generate correct cfg files.
Thanks
We were able to get the system to boot and the console issue figured out. Our solution brought up another question. The only way we were able to get the system to boot was to pull the JTAG_TRST_N signal from the module low for a moment. If my understanding is correct, this essentially reset the TX2 module. We couldn’t find in the power up documentation where it mentioned this was required.
What does this signal do?
How do we properly attach this signal to ensure automatic boot up?
Thanks
JTAG_TRST_N should be default low and no need to pull low manually. It looks like your design make it high during boot and so system can’t boot up. Suggest to compare your design with OEM guide/carrier board schematic to find out the difference which might cause this failure.
That fixed it. I was able to remove the pullup to the 1.8V rail. As soon as I did that boots up no problem.
Thanks,
We are unable to see the SATA disk drive on our carrier board. We get the following values when we read the status registers at base address 0x03507000.
Register Offset ReferenceKit OurCarrier
T_AHCI_HBA_GHC 0x4 0x80000002 0xFFFFFFFF
T_AHCI_PORT_PXIS 0x110 0x00000000 0xFFFFFFFF
T_AHCI_PORT_PXTFD 0x120 0x00000050 0xFFFFFFFF
T_AHCI_PORT_PXSSTS 0x128 0x00000123 0xFFFFFFFF
T_AHCI_PORT_PXSERR 0x130 0x00000000 0xFFFFFFFF
We also notice a small offset of about 400mV on the Tx+ and Tx- signals on the reference board that we do not see on our carrier board.
We did not connect the SATA_DEV_SLP signal on our carrier board.
Can you suggest some possible reasons why we don’t see the SATA drive?
We are also not seeing any USB devices. Could they be related?
Thank you very much for you help!
Hi, the device detection will not be affected if no SATA_DVE_SLP, please refer to this topic: [url]https://devtalk.nvidia.com/default/topic/1031786/?comment=5255616[/url]
Did you check the power sequence, strapping pins and unused pins configuration? What’t the difference on USB/SATA part between your design and reference board? Is the impedance matching of high speed IO checked? If your module works well with dev kit carrier board but not with custom board, then it looks like a hardware design issue.
Trumany,
The power sequencing is correct. The TX2 module is up and running. We can navigate the module using the console port (UART0). We’ve been able to successfully connect the Ethernet port. The only strapping pins we see are in relation to the booting of the module (Force Recovery, boundary scan mode). Are there others we are not aware of?
Through busybox (through console) we were able to read the registers for 0x03507000 as per the link you provided. All registers returned a 0XFFFFFFFF.
The only difference between the reference board and our schematic is a mux. I’ve attached the block diagram of our system. However, in efforts to more closely match the reference, we’ve removed the mux and wired directly to the SATA connector. Another thing we see which doesn’t match is on the referece board we see at 400mV offset on the SOM side of the TX+/TX- caps. On our board we do not see this offset. We theorize that the SATA subsystem is not coming up on the SOM, driving the offset. Thoughts?
While checking for signal we were able to see a series of 6 burst, which we assume is the OOB from the aforementioned link. However, we are only seeing them on the RX lines coming from the SSD. Why are we not seeing these on the TX lines?