Jetson AGX Xavier MIPI CSI-2 without I2C from FPGA

Hello NVIDIA Developers,

I would like to be able to use a Jetson AGX Xavier running L4T 32.4.4 to read a 4-lane MIPI CSI-2 without I2C from a Xilinx FGPA. The video is 1920 x 1080, 30fps, YUV444. The MIPI signals are sent from the FMC block of the FPGA to a Leopard Imaging LI-JXAV-MIPI-ADPT-4CAM adapter (https://www.leopardimaging.com/product/accessories/adapters-carrier-boards/li-jxav-mipi-adpt-4cam/).

Only one of the connectors on the Leopard board (J1) is being utilized during this phase of development. Multiple “cameras” will later be connected to the Leopard board, requiring enhancement to the dtsi files (e.g., similar to e3333 configuration). The electrical signals have been probed at the MIPI connector on the bottom of the Leopard board, and have been found to be good to the point where it makes physical contact with the Xavier. When the Leopard board is connected to the Xavier, i2cdetect -y -a -r 2 shows responses on addresses 0x54 and 0x70, but i2cdump on those addresses doesn’t seem to output anything meaningful. The i2cdetect and i2cdump commands yield the same respective results when the Leopard board while it is still connected to the Xavier, but disconnected from the FPGA.

The primary problem at this point is that the Xavier cannot detect /dev/video0.

I have gone through the NVIDIA development documentation (Sensor Software Driver Programming Guide, @JerryChang tutorial videos, etc.), and browsed through similar forum threads without success. Forum thread Xavier - using raw CSI without i2c appears to be the most similar problem, as my driver development was also initially based on the imx185 sensor (without success), but have since abandoned it in favor of using the ov5693 sensor files as my template after reading suggestions from @ShaneCCC.

As an aside, I pulled an ov5693 camera from a TX2 and captured streams successfully on the Xavier, so there shouldn’t be anything wrong with the pins on the Xavier MIPI port, or any fundamental problems with the Xavier itself.

Here is the recipe I last used to try to get this to work.


1. Edit tegra194-camera-e3326-a00.dtsi.

Only one mode is being used, which is set to 1920 x 1080 resolution.

/*
 * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/ {
	host1x {
		vi@15c10000 {
			num-channels = <1>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					reg = <0>;
					e3326_vi_in0: endpoint {
						port-index = <2>;
						bus-width = <4>;
						remote-endpoint = <&e3326_csi_out0>;
					};
				};
			};
		};

		nvcsi@15a00000 {
			num-channels = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
            status = "okay";
			channel@0 {
				reg = <0>;
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						reg = <0>;
						e3326_csi_in0: endpoint@0 {
							port-index = <2>;
							bus-width = <4>;
							remote-endpoint = <&e3326_ov5693_out0>;
						};
					};
					port@1 {
						reg = <1>;
						e3326_csi_out0: endpoint@1 {
							remote-endpoint = <&e3326_vi_in0>;
						};
					};
				};
			};
		};
	};

	i2c@3180000 {
		ov5693_c@36 {
			compatible = "nvidia,ov5693";
			/* I2C device address */
			reg = <0x36>;

			/* V4L2 device node location */
			devnode = "video0";

			/* Physical dimensions of sensor */
			physical_w = "3.674";
			physical_h = "2.738";

			/* Define any required hw resources needed by driver */
			/* ie. clocks, io pins, power sources */
			avdd-reg = "vana";
			iovdd-reg = "vif";

			/* Sensor output flip settings */
			vertical-flip = "true";

			/**
			* A modeX node is required to support v4l2 driver
			* implementation with NVIDIA camera software stack
			*
			* mclk_khz = "";
			* Standard MIPI driving clock, typically 24MHz
			*
			* num_lanes = "";
			* Number of lane channels sensor is programmed to output
			*
			* tegra_sinterface = "";
			* The base tegra serial interface lanes are connected to
			* Incase of virtual HW devices, use virtual
			* For SW emulated devices, use host
			*
			* phy_mode = "";
			* PHY mode used by the MIPI lanes for this device
			*
			* discontinuous_clk = "";
			* The sensor is programmed to use a discontinuous clock on MIPI lanes
			*
			* dpcm_enable = "true";
			* The sensor is programmed to use a DPCM modes
			*
			* cil_settletime = "";
			* MIPI lane settle time value.
			* A "0" value attempts to autocalibrate based on mclk_multiplier
			*
			*
			*
			*
			* active_w = "";
			* Pixel active region width
			*
			* active_h = "";
			* Pixel active region height
			*
			* pixel_t = "";
			* The sensor readout pixel pattern
			*
			* readout_orientation = "0";
			* Based on camera module orientation.
			* Only change readout_orientation if you specifically
			* Program a different readout order for this mode
			*
			* line_length = "";
			* Pixel line length (width) for sensor mode.
			* This is used to calibrate features in our camera stack.
			*
			* mclk_multiplier = "";
			* Multiplier to MCLK to help time hardware capture sequence
			* TODO: Assign to PLL_Multiplier as well until fixed in core
			*
			* pix_clk_hz = "";
			* Sensor pixel clock used for calculations like exposure and framerate
			*
			*
			*
			*
			* inherent_gain = "";
			* Gain obtained inherently from mode (ie. pixel binning)
			*
			* == Source Control Settings ==
			*
			* Gain factor used to convert fixed point integer to float
			* Gain range [min_gain/gain_factor, max_gain/gain_factor]
			* Gain step [step_gain/gain_factor is the smallest step that can be configured]
			* Default gain [Default gain to be initialized for the control.
			*     use min_gain_val as default for optimal results]
			* Framerate factor used to convert fixed point integer to float
			* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
			* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
			* Default Framerate [Default framerate to be initialized for the control.
			*     use max_framerate to get required performance]
			* Exposure factor used to convert fixed point integer to float
			* For convenience use 1 sec = 1000000us as conversion factor
			* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
			* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
			* Default Exposure Time [Default exposure to be initialized for the control.
			*     Set default exposure based on the default_framerate for optimal exposure settings]
			*
			* gain_factor = ""; (integer factor used for floating to fixed point conversion)
			* min_gain_val = ""; (ceil to integer)
			* max_gain_val = ""; (ceil to integer)
			* step_gain_val = ""; (ceil to integer)
			* default_gain = ""; (ceil to integer)
			* Gain limits for mode
			*
			* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
			* min_exp_time = ""; (ceil to integer)
			* max_exp_time = ""; (ceil to integer)
			* step_exp_time = ""; (ceil to integer)
			* default_exp_time = ""; (ceil to integer)
			* Exposure Time limits for mode (us)
			*
			*
			* min_hdr_ratio = "";
			* max_hdr_ratio = "";
			* HDR Ratio limits for mode
			*
			* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
			* min_framerate = "";
			* max_framerate = "";
			* step_framerate = ""; (ceil to integer)
			* default_framerate = ""; (ceil to integer)
			* Framerate limits for mode (fps)
			*/
			mode0 { // OV5693_MODE_2592X1944
				mclk_khz = "24000";
				num_lanes = "4";
				tegra_sinterface = "serial_c";
				phy_mode = "DPHY";
				discontinuous_clk = "yes";
				dpcm_enable = "false";
				cil_settletime = "0";

				active_w = "1920";
				active_h = "1080";
				mode_type = "bayer";
				pixel_phase = "rggb";
				csi_pixel_bit_depth = "8";
				readout_orientation = "0";
				line_length = "2688";
				inherent_gain = "1";
				mclk_multiplier = "6.67";
				pix_clk_hz = "160000000";

				gain_factor = "10";
				min_gain_val = "10";/* 1DB*/
				max_gain_val = "160";/* 16DB*/
				step_gain_val = "1";
				default_gain = "10";
				min_hdr_ratio = "1";
				max_hdr_ratio = "1";
				framerate_factor = "1000000";
				min_framerate = "1816577";/*1.816577 */
				max_framerate = "30000000";/*30*/
				step_framerate = "1";
				default_framerate = "30000000";
				exposure_factor = "1000000";
				min_exp_time = "34";/* us */
				max_exp_time = "550385";/* us */
				step_exp_time = "1";
				default_exp_time = "33334";/* us */
				embedded_metadata_height = "0";
			};

//			mode1 { //OV5693_MODE_2592X1458
//				mclk_khz = "24000";
//				num_lanes = "2";
//				tegra_sinterface = "serial_c";
//				phy_mode = "DPHY";
//				discontinuous_clk = "yes";
//				dpcm_enable = "false";
//				cil_settletime = "0";
//
//				active_w = "2592";
//				active_h = "1458";
//				mode_type = "bayer";
//				pixel_phase = "bggr";
//				csi_pixel_bit_depth = "10";
//				readout_orientation = "0";
//				line_length = "2688";
//				inherent_gain = "1";
//				mclk_multiplier = "6.67";
//				pix_clk_hz = "160000000";
//
//				gain_factor = "10";
//				min_gain_val = "10";/* 1DB*/
//				max_gain_val = "160";/* 16DB*/
//				step_gain_val = "1";
//				default_gain = "10";
//				min_hdr_ratio = "1";
//				max_hdr_ratio = "1";
//				framerate_factor = "1000000";
//				min_framerate = "1816577";/*1.816577 */
//				max_framerate = "30000000";/*30*/
//				step_framerate = "1";
//				default_framerate = "30000000";
//				exposure_factor = "1000000";
//				min_exp_time = "34";/* us */
//				max_exp_time = "550385";/* us */
//				step_exp_time = "1";
//				default_exp_time = "33334";/* us */
//				embedded_metadata_height = "0";
//			};
//
//			mode2 { //OV5693_MODE_1280X720
//				mclk_khz = "24000";
//				num_lanes = "2";
//				tegra_sinterface = "serial_c";
//				phy_mode = "DPHY";
//				discontinuous_clk = "yes";
//				dpcm_enable = "false";
//				cil_settletime = "0";
//
//				active_w = "1280";
//				active_h = "720";
//				mode_type = "bayer";
//				pixel_phase = "bggr";
//				csi_pixel_bit_depth = "10";
//				readout_orientation = "0";
//				line_length = "1752";
//				inherent_gain = "1";
//				mclk_multiplier = "6.67";
//				pix_clk_hz = "160000000";
//
//				gain_factor = "10";
//				min_gain_val = "10";/* 1DB*/
//				max_gain_val = "160";/* 16DB*/
//				step_gain_val = "1";
//				default_gain = "10";
//				min_hdr_ratio = "1";
//				max_hdr_ratio = "1";
//				framerate_factor = "1000000";
//				min_framerate = "2787078";/* 2.787078 */
//				max_framerate = "120000000";/* 120*/
//				step_framerate = "1";
//				default_framerate = "120000000";
//				exposure_factor = "1000000";
//				min_exp_time = "22";/* us */
//				max_exp_time = "358733";/* us */
//				step_exp_time = "1";
//				default_exp_time = "8334";/* us */
//				embedded_metadata_height = "0";
//			};

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					e3326_ov5693_out0: endpoint {
						port-index = <2>;
						bus-width = <4>;
						remote-endpoint = <&e3326_csi_in0>;
					};
				};
			};
		};
	};

	e3326_lens_ov5693@P5V27C {
		min_focus_distance = "0.0";
		hyper_focal = "0.0";
		focal_length = "2.67";
		f_number = "2.0";
		aperture = "2.0";
	};

	tegra-camera-platform {
		compatible = "nvidia, tegra-camera-platform";
		/**
		* Physical settings to calculate max ISO BW
		*
		* num_csi_lanes = <>;
		* Total number of CSI lanes when all cameras are active
		*
		* max_lane_speed = <>;
		* Max lane speed in Kbit/s
		*
		* min_bits_per_pixel = <>;
		* Min bits per pixel
		*
		* vi_peak_byte_per_pixel = <>;
		* Max byte per pixel for the VI ISO case
		*
		* vi_bw_margin_pct = <>;
		* Vi bandwidth margin in percentage
		*
		* max_pixel_rate = <>;
		* Max pixel rate in Kpixel/s for the ISP ISO case
		*
		* isp_peak_byte_per_pixel = <>;
		* Max byte per pixel for the ISP ISO case
		*
		* isp_bw_margin_pct = <>;
		* Isp bandwidth margin in percentage
		*/
		num_csi_lanes = <4>;
		max_lane_speed = <1500000>;
		min_bits_per_pixel = <8>;
		vi_peak_byte_per_pixel = <2>;
		vi_bw_margin_pct = <25>;
		max_pixel_rate = <160000>;
		isp_peak_byte_per_pixel = <5>;
		isp_bw_margin_pct = <25>;

		/**
		* The general guideline for naming badge_info contains 3 parts, and is as follows,
		* The first part is the camera_board_id for the module; if the module is in a FFD
		* platform, then use the platform name for this part.
		* The second part contains the position of the module, ex. “rear” or “front”.
		* The third part contains the last 6 characters of a part number which is found
		* in the module's specsheet from the vender.
		*/
		modules {
			module0 {
				badge = "e3326_front_P5V27C";
				position = "rear";
				orientation = "1";
				drivernode0 {
					/* Declare PCL support driver (classically known as guid)  */
					pcl_id = "v4l2_sensor";
					/* Driver v4l2 device name */
					devname = "ov5693 2-0036";
					/* Declare the device-tree hierarchy to driver instance */
					proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_c@36";
				};
				drivernode1 {
					/* Declare PCL support driver (classically known as guid)  */
					pcl_id = "v4l2_lens";
					proc-device-tree = "/proc/device-tree/e3326_lens_ov5693@P5V27C/";
				};
			};
		};
	};
};

2. Edit tegra194-p2822-0000-camera-e3326-a00.dtsi

Edits to this file were very minimal, adding just one line of status = “okay”. This file is structured differently than the camera modules file that was originally used from the imx185 template, which leads into step #3.

/*
 * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <t19x-common-modules/tegra194-camera-e3326-a00.dtsi>
#include "dt-bindings/clock/tegra194-clock.h"

#define CAM0_RST_L	TEGRA194_MAIN_GPIO(H, 3)
#define CAM0_PWDN	TEGRA194_MAIN_GPIO(H, 6)

/* camera control gpio definitions */

/ {
	i2c@3180000 {
		ov5693_c@36 {
			/* Define any required hw resources needed by driver */
			/* ie. clocks, io pins, power sources */
			/* mclk-index indicates the index of the */
			/* mclk-name with in the clock-names array */

			clocks = <&bpmp_clks TEGRA194_CLK_EXTPERIPH1>,
					 <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
			clock-names = "extperiph1", "pllp_grtba";
			mclk = "extperiph1";
			clock-frequency = <24000000>;
			reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
			pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
			vana-supply = <&p2822_avdd_cam_2v8>;
			vif-supply = <&p2822_vdd_1v8_cvb>;

            status = "okay";
		};
	};

	gpio@2200000 {
		camera-control-output-low {
			gpio-hog;
			output-low;
			gpios = <CAM0_RST_L 0 CAM0_PWDN 0>;
			label = "cam0-rst", "cam0-pwdn";
		};
	};
};

3. Disable plugin manager.

Edited tegra194-p2888-0001-p2822-0000.dts. It was unclear to me if comments from @ShaneCCC regarding #include tegra194-p2822-0000-camera-e3326-a00.dtsi; statement refers to the file in its default state, or if the file requires additional edits.

/*
 * Top level DTS file for CVM:P2888-0001 and CVB:P2822-0000.
 *
 * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */
#include "common/tegra194-p2888-0001-p2822-0000-common.dtsi"
//#include "common/tegra194-p2822-camera-modules.dtsi"
//#include "t19x-common-modules/tegra194-camera-plugin-manager.dtsi"
#include "common/tegra194-p2822-0000-camera-e3326-a00.dtsi"

4. Edit ov5693.c.

I did not actually make any edits to this particular file. I just copied it from @ShaneCCC in forum thread Xavier - using raw CSI without i2c.

/*
 * ov5693_v4l2.c - ov5693 sensor driver
 *
 * Copyright (c) 2013-2019, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/debugfs.h>

#include <linux/seq_file.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <media/tegra-v4l2-camera.h>
#include <media/tegracam_core.h>
#include <media/ov5693.h>


#include "../platform/tegra/camera/camera_gpio.h"
#include "ov5693_mode_tbls.h"
#define CREATE_TRACE_POINTS
#include <trace/events/ov5693.h>

#define OV5693_MAX_COARSE_DIFF		6
#define OV5693_MAX_FRAME_LENGTH	(0x7fff)
#define OV5693_MIN_EXPOSURE_COARSE	(0x0002)
#define OV5693_MAX_EXPOSURE_COARSE	\
	(OV5693_MAX_FRAME_LENGTH-OV5693_MAX_COARSE_DIFF)
#define OV5693_DEFAULT_LINE_LENGTH	(0xA80)
#define OV5693_DEFAULT_PIXEL_CLOCK	(160)
#define OV5693_DEFAULT_FRAME_LENGTH	(0x07C0)
#define OV5693_DEFAULT_EXPOSURE_COARSE	\
	(OV5693_DEFAULT_FRAME_LENGTH-OV5693_MAX_COARSE_DIFF)

static const u32 ctrl_cid_list[] = {
	TEGRA_CAMERA_CID_GAIN,
	TEGRA_CAMERA_CID_EXPOSURE,
	TEGRA_CAMERA_CID_EXPOSURE_SHORT,
	TEGRA_CAMERA_CID_FRAME_RATE,
	TEGRA_CAMERA_CID_GROUP_HOLD,
	TEGRA_CAMERA_CID_HDR_EN,
};

struct ov5693 {
	struct i2c_client		*i2c_client;
	struct v4l2_subdev		*subdev;
	const char			*devname;
	struct mutex			streaming_lock;
	bool				streaming;

	s32				group_hold_prev;
	u32				frame_length;
	bool				group_hold_en;
	struct camera_common_i2c	i2c_dev;
	struct camera_common_data	*s_data;
	struct tegracam_device		*tc_dev;
};

static struct regmap_config ov5693_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
};

static inline void ov5693_get_frame_length_regs(ov5693_reg *regs,
				u32 frame_length)
{
	regs->addr = OV5693_FRAME_LENGTH_ADDR_MSB;
	regs->val = (frame_length >> 8) & 0xff;
	(regs + 1)->addr = OV5693_FRAME_LENGTH_ADDR_LSB;
	(regs + 1)->val = (frame_length) & 0xff;
}

static inline void ov5693_get_coarse_time_regs(ov5693_reg *regs,
				u32 coarse_time)
{
	regs->addr = OV5693_COARSE_TIME_ADDR_1;
	regs->val = (coarse_time >> 12) & 0xff;
	(regs + 1)->addr = OV5693_COARSE_TIME_ADDR_2;
	(regs + 1)->val = (coarse_time >> 4) & 0xff;
	(regs + 2)->addr = OV5693_COARSE_TIME_ADDR_3;
	(regs + 2)->val = (coarse_time & 0xf) << 4;
}

static inline void ov5693_get_coarse_time_short_regs(ov5693_reg *regs,
				u32 coarse_time)
{
	regs->addr = OV5693_COARSE_TIME_SHORT_ADDR_1;
	regs->val = (coarse_time >> 12) & 0xff;
	(regs + 1)->addr = OV5693_COARSE_TIME_SHORT_ADDR_2;
	(regs + 1)->val = (coarse_time >> 4) & 0xff;
	(regs + 2)->addr = OV5693_COARSE_TIME_SHORT_ADDR_3;
	(regs + 2)->val = (coarse_time & 0xf) << 4;
}

static inline void ov5693_get_gain_regs(ov5693_reg *regs,
				u16 gain)
{
	regs->addr = OV5693_GAIN_ADDR_MSB;
	regs->val = (gain >> 8) & 0xff;

	(regs + 1)->addr = OV5693_GAIN_ADDR_LSB;
	(regs + 1)->val = (gain) & 0xff;
}

static int test_mode;
module_param(test_mode, int, 0644);

static int ov5693_write_reg(struct camera_common_data *s_data, u16 addr, u8 val)
{
	return 0;
}

static int ov5693_write_table(struct ov5693 *priv,
			      const ov5693_reg table[])
{
	return 0;
}

static void ov5693_gpio_set(struct camera_common_data *s_data,
			    unsigned int gpio, int val)
{
	struct camera_common_pdata *pdata = s_data->pdata;

	if (pdata && pdata->use_cam_gpio)
		cam_gpio_ctrl(s_data->dev, gpio, val, 1);
	else {
		if (gpio_cansleep(gpio))
			gpio_set_value_cansleep(gpio, val);
		else
			gpio_set_value(gpio, val);
	}
}

static int ov5693_power_on(struct camera_common_data *s_data)
{
	int err = 0;
	struct camera_common_power_rail *pw = s_data->power;
	struct camera_common_pdata *pdata = s_data->pdata;
	struct device *dev = s_data->dev;


	dev_dbg(dev, "%s: power on\n", __func__);

	if (pdata && pdata->power_on) {
		err = pdata->power_on(pw);
		if (err)
			dev_err(dev, "%s failed.\n", __func__);
		else
			pw->state = SWITCH_ON;
		return err;
	}
	/* sleeps calls in the sequence below are for internal device
	 * signal propagation as specified by sensor vendor
	 */

	if (pw->avdd)
		err = regulator_enable(pw->avdd);
	if (err)
		goto ov5693_avdd_fail;

	if (pw->iovdd)
		err = regulator_enable(pw->iovdd);
	if (err)
		goto ov5693_iovdd_fail;

	usleep_range(1, 2);
	if (gpio_is_valid(pw->pwdn_gpio))
		ov5693_gpio_set(s_data, pw->pwdn_gpio, 1);

	/*
	 * datasheet 2.9: reset requires ~2ms settling time
	 * a power on reset is generated after core power becomes stable
	 */
	usleep_range(2000, 2010);

	if (gpio_is_valid(pw->reset_gpio))
		ov5693_gpio_set(s_data, pw->reset_gpio, 1);

	/* datasheet fig 2-9: t3 */
	usleep_range(2000, 2010);

	pw->state = SWITCH_ON;


	return 0;

ov5693_iovdd_fail:
	regulator_disable(pw->avdd);

ov5693_avdd_fail:
	dev_err(dev, "%s failed.\n", __func__);
	return -ENODEV;
}

static int ov5693_power_off(struct camera_common_data *s_data)
{
	int err = 0;
	struct camera_common_power_rail *pw = s_data->power;
	struct device *dev = s_data->dev;
	struct camera_common_pdata *pdata = s_data->pdata;

	dev_dbg(dev, "%s: power off\n", __func__);

	if (pdata && pdata->power_off) {
		err = pdata->power_off(pw);
		if (!err) {
			goto power_off_done;
		} else {
			dev_err(dev, "%s failed.\n", __func__);
			return err;
		}
	}

	/* sleeps calls in the sequence below are for internal device
	 * signal propagation as specified by sensor vendor
	 */
	usleep_range(21, 25);
	if (gpio_is_valid(pw->pwdn_gpio))
		ov5693_gpio_set(s_data, pw->pwdn_gpio, 0);
	usleep_range(1, 2);
	if (gpio_is_valid(pw->reset_gpio))
		ov5693_gpio_set(s_data, pw->reset_gpio, 0);

	/* datasheet 2.9: reset requires ~2ms settling time*/
	usleep_range(2000, 2010);

	if (pw->iovdd)
		regulator_disable(pw->iovdd);
	if (pw->avdd)
		regulator_disable(pw->avdd);

power_off_done:
	pw->state = SWITCH_OFF;
	return 0;
}

static int ov5693_power_put(struct tegracam_device *tc_dev)
{
	struct camera_common_data *s_data = tc_dev->s_data;
	struct camera_common_power_rail *pw = s_data->power;
	struct camera_common_pdata *pdata = s_data->pdata;
	struct device *dev = tc_dev->dev;

	if (unlikely(!pw))
		return -EFAULT;

	if (pdata && pdata->use_cam_gpio)
		cam_gpio_deregister(dev, pw->pwdn_gpio);
	else {
		if (gpio_is_valid(pw->pwdn_gpio))
			gpio_free(pw->pwdn_gpio);
		if (gpio_is_valid(pw->reset_gpio))
			gpio_free(pw->reset_gpio);
	}

	return 0;
}

static int ov5693_power_get(struct tegracam_device *tc_dev)
{
	struct camera_common_data *s_data = tc_dev->s_data;
	struct camera_common_power_rail *pw = s_data->power;
	struct camera_common_pdata *pdata = s_data->pdata;
	struct device *dev = tc_dev->dev;
	const char *mclk_name;
	const char *parentclk_name;
	struct clk *parent;
	int err = 0, ret = 0;

	if (!pdata) {
		dev_err(dev, "pdata missing\n");
		return -EFAULT;
	}

	mclk_name = pdata->mclk_name ?
		    pdata->mclk_name : "cam_mclk1";
	pw->mclk = devm_clk_get(dev, mclk_name);
	if (IS_ERR(pw->mclk)) {
		dev_err(dev, "unable to get clock %s\n", mclk_name);
		return PTR_ERR(pw->mclk);
	}
	parentclk_name = pdata->parentclk_name;
	if (parentclk_name) {
		parent = devm_clk_get(dev, parentclk_name);
		if (IS_ERR(parent)) {
			dev_err(dev, "unable to get parent clcok %s",
				parentclk_name);
		} else
			clk_set_parent(pw->mclk, parent);
	}

	/* analog 2.8v */
	err |= camera_common_regulator_get(dev,
			&pw->avdd, pdata->regulators.avdd);
	/* IO 1.8v */
	err |= camera_common_regulator_get(dev,
			&pw->iovdd, pdata->regulators.iovdd);

	if (!err) {
		pw->reset_gpio = pdata->reset_gpio;
		pw->pwdn_gpio = pdata->pwdn_gpio;
	}
	if (pdata->use_cam_gpio) {
		err = cam_gpio_register(dev, pw->pwdn_gpio);
		if (err)
			dev_err(dev, "%s ERR can't register cam gpio %u!\n",
				 __func__, pw->pwdn_gpio);
	} else {
		if (gpio_is_valid(pw->pwdn_gpio)) {
			ret = gpio_request(pw->pwdn_gpio, "cam_pwdn_gpio");
			if (ret < 0) {
				dev_dbg(dev, "%s can't request pwdn_gpio %d\n",
					__func__, ret);
			}
			gpio_direction_output(pw->pwdn_gpio, 1);
		}
		if (gpio_is_valid(pw->reset_gpio)) {
			ret = gpio_request(pw->reset_gpio, "cam_reset_gpio");
			if (ret < 0) {
				dev_dbg(dev, "%s can't request reset_gpio %d\n",
					__func__, ret);
			}
			gpio_direction_output(pw->reset_gpio, 1);
		}
	}

	pw->state = SWITCH_OFF;
	return err;
}

static int ov5693_set_gain(struct tegracam_device *tc_dev, s64 val);
static int ov5693_set_frame_rate(struct tegracam_device *tc_dev, s64 val);
static int ov5693_set_exposure(struct tegracam_device *tc_dev, s64 val);
static int ov5693_set_exposure_short(struct tegracam_device *tc_dev, s64 val);

static const struct of_device_id ov5693_of_match[] = {
	{
		.compatible = "nvidia,ov5693",
	},
	{ },
};

static int ov5693_set_group_hold(struct tegracam_device *tc_dev, bool val)
{
	int err;
	struct ov5693 *priv = tc_dev->priv;
	int gh_prev = switch_ctrl_qmenu[priv->group_hold_prev];
	struct device *dev = tc_dev->dev;

	if (priv->group_hold_en == true && gh_prev == SWITCH_OFF) {
		camera_common_i2c_aggregate(&priv->i2c_dev, true);
		/* enter group hold */
		err = ov5693_write_reg(priv->s_data,
				       OV5693_GROUP_HOLD_ADDR, val);
		if (err)
			goto fail;

		priv->group_hold_prev = 1;

		dev_dbg(dev, "%s: enter group hold\n", __func__);
	} else if (priv->group_hold_en == false && gh_prev == SWITCH_ON) {
		/* leave group hold */
		err = ov5693_write_reg(priv->s_data,
				       OV5693_GROUP_HOLD_ADDR, 0x11);
		if (err)
			goto fail;

		err = ov5693_write_reg(priv->s_data,
				       OV5693_GROUP_HOLD_ADDR, 0x61);
		if (err)
			goto fail;

		priv->group_hold_prev = 0;

		dev_dbg(dev, "%s: leave group hold\n", __func__);
	}

	return 0;

fail:
	dev_dbg(dev, "%s: Group hold control error\n", __func__);
	return err;
}

static int ov5693_set_gain(struct tegracam_device *tc_dev, s64 val)
{
	struct camera_common_data *s_data = tc_dev->s_data;
	struct ov5693 *priv = (struct ov5693 *)tc_dev->priv;
	struct device *dev = tc_dev->dev;
	const struct sensor_mode_properties *mode =
		&s_data->sensor_props.sensor_modes[s_data->mode_prop_idx];
	ov5693_reg reg_list[2];
	int err;
	u16 gain;
	int i;

	if (!priv->group_hold_prev)
		ov5693_set_group_hold(tc_dev, 1);

	/* translate value */
	gain = (u16) (((val * 16) +
			(mode->control_properties.gain_factor / 2)) /
			mode->control_properties.gain_factor);
	ov5693_get_gain_regs(reg_list, gain);
	dev_dbg(dev, "%s: gain %d val: %lld\n", __func__, gain, val);

	for (i = 0; i < 2; i++) {
		err = ov5693_write_reg(s_data, reg_list[i].addr,
			 reg_list[i].val);
		if (err)
			goto fail;
	}

	return 0;

fail:
	dev_dbg(dev, "%s: GAIN control error\n", __func__);
	return err;
}

static int ov5693_set_frame_rate(struct tegracam_device *tc_dev, s64 val)
{
	struct camera_common_data *s_data = tc_dev->s_data;
	struct device *dev = tc_dev->dev;
	struct ov5693 *priv = tc_dev->priv;
	const struct sensor_mode_properties *mode =
		&s_data->sensor_props.sensor_modes[s_data->mode_prop_idx];
	ov5693_reg reg_list[2];
	int err;
	u32 frame_length;
	int i;

	if (!priv->group_hold_prev)
		ov5693_set_group_hold(tc_dev, 1);

	frame_length =  mode->signal_properties.pixel_clock.val *
		mode->control_properties.framerate_factor /
		mode->image_properties.line_length / val;

	ov5693_get_frame_length_regs(reg_list, frame_length);
	dev_dbg(dev, "%s: val: %d\n", __func__, frame_length);

	for (i = 0; i < 2; i++) {
		err = ov5693_write_reg(s_data, reg_list[i].addr,
			 reg_list[i].val);
		if (err)
			goto fail;
	}

	priv->frame_length = frame_length;

	return 0;

fail:
	dev_dbg(dev, "%s: FRAME_LENGTH control error\n", __func__);
	return err;
}

static int ov5693_set_exposure(struct tegracam_device *tc_dev, s64 val)
{
	struct camera_common_data *s_data = tc_dev->s_data;
	struct device *dev = tc_dev->dev;
	struct ov5693 *priv = tc_dev->priv;
	const s32 max_coarse_time = priv->frame_length - OV5693_MAX_COARSE_DIFF;
	const struct sensor_mode_properties *mode =
		&s_data->sensor_props.sensor_modes[s_data->mode_prop_idx];
	ov5693_reg reg_list[3];
	int err;
	u32 coarse_time;
	int i;

	if (!priv->group_hold_prev)
		ov5693_set_group_hold(tc_dev, 1);

	coarse_time = (u32)(((mode->signal_properties.pixel_clock.val*val)
			/mode->image_properties.line_length)/
			mode->control_properties.exposure_factor);
	if (coarse_time < OV5693_MIN_EXPOSURE_COARSE)
		coarse_time = OV5693_MIN_EXPOSURE_COARSE;
	else if (coarse_time > max_coarse_time)
		coarse_time = max_coarse_time;
	ov5693_get_coarse_time_regs(reg_list, coarse_time);
	dev_dbg(dev, "%s: val: %d\n", __func__, coarse_time);

	for (i = 0; i < 3; i++) {
		err = ov5693_write_reg(s_data, reg_list[i].addr,
			 reg_list[i].val);
		if (err)
			goto fail;
	}

	return 0;

fail:
	dev_dbg(dev, "%s: COARSE_TIME control error\n", __func__);
	return err;
}

static int ov5693_set_exposure_short(struct tegracam_device *tc_dev, s64 val)
{
	struct camera_common_data *s_data = tc_dev->s_data;
	struct device *dev = tc_dev->dev;
	struct ov5693 *priv = tc_dev->priv;
	const struct sensor_mode_properties *mode =
		&s_data->sensor_props.sensor_modes[s_data->mode_prop_idx];
	ov5693_reg reg_list[3];
	int err;
	struct v4l2_control hdr_control;
	int hdr_en;
	u32 coarse_time_short;
	int i;
	if (!priv->group_hold_prev)
		ov5693_set_group_hold(tc_dev, 1);

	/* check hdr enable ctrl */
	hdr_control.id = TEGRA_CAMERA_CID_HDR_EN;

	err = camera_common_g_ctrl(s_data, &hdr_control);
	if (err < 0) {
		dev_err(dev, "could not find device ctrl.\n");
		return err;
	}

	hdr_en = switch_ctrl_qmenu[hdr_control.value];
	if (hdr_en == SWITCH_OFF)
		return 0;

	coarse_time_short = (u32)(((mode->signal_properties.pixel_clock.val*val)
				/mode->image_properties.line_length)
				/mode->control_properties.exposure_factor);

	ov5693_get_coarse_time_short_regs(reg_list, coarse_time_short);
	dev_dbg(dev, "%s: val: %d\n", __func__, coarse_time_short);

	for (i = 0; i < 3; i++) {
		err = ov5693_write_reg(s_data, reg_list[i].addr,
			 reg_list[i].val);
		if (err)
			goto fail;
	}

	return 0;

fail:
	dev_dbg(dev, "%s: COARSE_TIME_SHORT control error\n", __func__);
	return err;
}

MODULE_DEVICE_TABLE(of, ov5693_of_match);

static struct camera_common_pdata *ov5693_parse_dt(struct tegracam_device
							*tc_dev)
{
	struct device *dev = tc_dev->dev;
	struct device_node *node = dev->of_node;
	struct camera_common_pdata *board_priv_pdata;
	const struct of_device_id *match;
	int gpio;
	int err;
	struct camera_common_pdata *ret = NULL;

	if (!node)
		return NULL;

	match = of_match_device(ov5693_of_match, dev);
	if (!match) {
		dev_err(dev, "Failed to find matching dt id\n");
		return NULL;
	}

	board_priv_pdata = devm_kzalloc(dev,
			   sizeof(*board_priv_pdata), GFP_KERNEL);
	if (!board_priv_pdata)
		return NULL;

	err = camera_common_parse_clocks(dev,
					 board_priv_pdata);
	if (err) {
		dev_err(dev, "Failed to find clocks\n");
		goto error;
	}

	gpio = of_get_named_gpio(node, "pwdn-gpios", 0);
	if (gpio < 0) {
		if (gpio == -EPROBE_DEFER) {
			ret = ERR_PTR(-EPROBE_DEFER);
			goto error;
		}
		gpio = 0;
	}
	board_priv_pdata->pwdn_gpio = (unsigned int)gpio;

	gpio = of_get_named_gpio(node, "reset-gpios", 0);
	if (gpio < 0) {
		/* reset-gpio is not absolutely needed */
		if (gpio == -EPROBE_DEFER) {
			ret = ERR_PTR(-EPROBE_DEFER);
			goto error;
		}
		dev_dbg(dev, "reset gpios not in DT\n");
		gpio = 0;
	}
	board_priv_pdata->reset_gpio = (unsigned int)gpio;

	board_priv_pdata->use_cam_gpio =
		of_property_read_bool(node, "cam, use-cam-gpio");

	err = of_property_read_string(node, "avdd-reg",
			&board_priv_pdata->regulators.avdd);
	if (err) {
		dev_err(dev, "avdd-reg not in DT\n");
		goto error;
	}
	err = of_property_read_string(node, "iovdd-reg",
			&board_priv_pdata->regulators.iovdd);
	if (err) {
		dev_err(dev, "iovdd-reg not in DT\n");
		goto error;
	}

	board_priv_pdata->v_flip = of_property_read_bool(node, "vertical-flip");
	board_priv_pdata->h_mirror = of_property_read_bool(node,
							 "horizontal-mirror");

	return board_priv_pdata;

error:
	devm_kfree(dev, board_priv_pdata);
	return ret;
}

static int ov5693_set_mode(struct tegracam_device *tc_dev)
{
	struct ov5693 *priv = (struct ov5693 *)tegracam_get_privdata(tc_dev);
	struct camera_common_data *s_data = tc_dev->s_data;
	int err;

	err = ov5693_write_table(priv, mode_table[s_data->mode_prop_idx]);
	if (err)
		return err;

	return 0;
}

static int ov5693_start_streaming(struct tegracam_device *tc_dev)
{
	struct ov5693 *priv = (struct ov5693 *)tegracam_get_privdata(tc_dev);

	mutex_lock(&priv->streaming_lock);
	priv->streaming = true;
	mutex_unlock(&priv->streaming_lock);

	return 0;
}

static int ov5693_stop_streaming(struct tegracam_device *tc_dev)
{
	struct ov5693 *priv = (struct ov5693 *)tegracam_get_privdata(tc_dev);
	u32 frame_time;

	mutex_lock(&priv->streaming_lock);
	priv->streaming = false;
	mutex_unlock(&priv->streaming_lock);

	/*
	 * Wait for one frame to make sure sensor is set to
	 * software standby in V-blank
	 *
	 * frame_time = frame length rows * Tline
	 * Tline = line length / pixel clock (in MHz)
	 */
	frame_time = priv->frame_length *
		OV5693_DEFAULT_LINE_LENGTH / OV5693_DEFAULT_PIXEL_CLOCK;

	usleep_range(frame_time, frame_time + 1000);

	return 0;
}

static struct camera_common_sensor_ops ov5693_common_ops = {
	.numfrmfmts = ARRAY_SIZE(ov5693_frmfmt),
	.frmfmt_table = ov5693_frmfmt,
	.power_on = ov5693_power_on,
	.power_off = ov5693_power_off,
	.write_reg = ov5693_write_reg,
	.parse_dt = ov5693_parse_dt,
	.power_get = ov5693_power_get,
	.power_put = ov5693_power_put,
	.set_mode = ov5693_set_mode,
	.start_streaming = ov5693_start_streaming,
	.stop_streaming = ov5693_stop_streaming,
};

static struct tegracam_ctrl_ops ov5693_ctrl_ops = {
	.numctrls = ARRAY_SIZE(ctrl_cid_list),
	.ctrl_cid_list = ctrl_cid_list,
	.set_gain = ov5693_set_gain,
	.set_exposure = ov5693_set_exposure,
	.set_exposure_short = ov5693_set_exposure_short,
	.set_frame_rate = ov5693_set_frame_rate,
	.set_group_hold = ov5693_set_group_hold,
};

static int ov5693_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	dev_dbg(&client->dev, "%s:\n", __func__);
	return 0;
}

static const struct v4l2_subdev_internal_ops ov5693_subdev_internal_ops = {
	.open = ov5693_open,
};

static int ov5693_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	struct device *dev = &client->dev;
	struct device_node *node = client->dev.of_node;
	struct tegracam_device *tc_dev;
	struct ov5693 *priv;
	int err;
	const struct of_device_id *match;

	dev_info(dev, "probing v4l2 sensor no i2c.\n");

	match = of_match_device(ov5693_of_match, dev);
	if (!match) {
		dev_err(dev, "No device match found\n");
		return -ENODEV;
	}

	if (!IS_ENABLED(CONFIG_OF) || !node)
		return -EINVAL;

	priv = devm_kzalloc(dev,
			    sizeof(struct ov5693), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	tc_dev = devm_kzalloc(dev,
			    sizeof(struct tegracam_device), GFP_KERNEL);
	if (!tc_dev)
		return -ENOMEM;

	priv->i2c_client = tc_dev->client = client;
	tc_dev->dev = dev;
	strncpy(tc_dev->name, "ov5693", sizeof(tc_dev->name));
	tc_dev->dev_regmap_config = &ov5693_regmap_config;
	tc_dev->sensor_ops = &ov5693_common_ops;
	tc_dev->v4l2sd_internal_ops = &ov5693_subdev_internal_ops;
	tc_dev->tcctrl_ops = &ov5693_ctrl_ops;

	err = tegracam_device_register(tc_dev);
	if (err) {
		dev_err(dev, "tegra camera driver registration failed\n");
		return err;
	}

	priv->tc_dev = tc_dev;
	priv->s_data = tc_dev->s_data;
	priv->subdev = &tc_dev->s_data->subdev;
	tegracam_set_privdata(tc_dev, (void *)priv);
	mutex_init(&priv->streaming_lock);

	err = tegracam_v4l2subdev_register(tc_dev, true);
	if (err) {
		dev_err(dev, "tegra camera subdev registration failed\n");
		return err;
	}

	dev_dbg(dev, "Detected OV5693 sensor\n");

	return 0;
}

static int
ov5693_remove(struct i2c_client *client)
{
	struct camera_common_data *s_data = to_camera_common_data(&client->dev);
	struct ov5693 *priv = (struct ov5693 *)s_data->priv;

	tegracam_v4l2subdev_unregister(priv->tc_dev);
	ov5693_power_put(priv->tc_dev);
	tegracam_device_unregister(priv->tc_dev);

	mutex_destroy(&priv->streaming_lock);

	return 0;
}

static const struct i2c_device_id ov5693_id[] = {
	{ "ov5693", 0 },
	{ }
};

MODULE_DEVICE_TABLE(i2c, ov5693_id);

static struct i2c_driver ov5693_i2c_driver = {
	.driver = {
		.name = "ov5693",
		.owner = THIS_MODULE,
		.of_match_table = of_match_ptr(ov5693_of_match),
	},
	.probe = ov5693_probe,
	.remove = ov5693_remove,
	.id_table = ov5693_id,
};
module_i2c_driver(ov5693_i2c_driver);

MODULE_DESCRIPTION("Media Controller driver for OmniVision OV5693");
MODULE_AUTHOR("NVIDIA Corporation");
MODULE_LICENSE("GPL v2");

5. Edit ov5693_mode_tbls.h.

Like the file above, I just picked this up from @ShaneCCC in forum thread Xavier - using raw CSI without i2c. The only edit I made was to the mode table for 1920 x 1080 resolution.

/*
 * ov5693_mode_tbls.h - ov5693 sensor mode tables
 *
 * Copyright (c) 2015-2019, NVIDIA CORPORATION, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __OV5693_TABLES__
#define __OV5693_TABLES__

#include <media/camera_common.h>

#define OV5693_TABLE_WAIT_MS	0
#define OV5693_TABLE_END	1
#define OV5693_MAX_RETRIES	3
#define OV5693_WAIT_MS		10

#define ov5693_reg struct reg_8

static const ov5693_reg ov5693_start[] = {
	{0x0100, 0x01}, /* mode select streaming on */
	{OV5693_TABLE_END, 0x00}
};

static const ov5693_reg ov5693_stop[] = {
	{0x0100, 0x00}, /* mode select streaming on */
	{OV5693_TABLE_END, 0x00}
};

static const ov5693_reg tp_colorbars[] = {
	{0x0600, 0x00},
	{0x0601, 0x02},

	{OV5693_TABLE_WAIT_MS, OV5693_WAIT_MS},
	{OV5693_TABLE_END, 0x00}
};

static const ov5693_reg mode_2592x1944[] = {
	{OV5693_TABLE_WAIT_MS, OV5693_WAIT_MS},
	{OV5693_TABLE_END, 0x0000}
};

enum {
	OV5693_MODE_2592X1944,

	OV5693_MODE_START_STREAM,
	OV5693_MODE_STOP_STREAM,
	OV5693_MODE_TEST_PATTERN
};

static const ov5693_reg *mode_table[] = {
	[OV5693_MODE_2592X1944]			= mode_2592x1944,

	[OV5693_MODE_START_STREAM]		= ov5693_start,
	[OV5693_MODE_STOP_STREAM]		= ov5693_stop,
	[OV5693_MODE_TEST_PATTERN]		= tp_colorbars,
};

static const int ov5693_30fps[] = {
	30,
};

static const struct camera_common_frmfmt ov5693_frmfmt[] = {
	{{1920, 1080},	ov5693_30fps,	1, 0,	OV5693_MODE_2592X1944},
};
#endif  /* __OV5693_TABLES__ */

6. Kernel configuration.

Edited [src]/kernel/kernel-4.9/arch/arm64/configs/tegra_defconfig.

CONFIG_VIDEO_OV5693=y

Note: In previous iterations, this step was also tried as a loadable kernel module by changing the line to CONFIG_VIDEO_OV5693=m, copying the new LKM file to the jetson, then running $ sudo rmmod [path_to_original_ov5693.ko], and finally $ sudo insmod [path_to_new_ov5693.ko]. This did not change anything in regard to the detection of /dev/video0.

7. Build the NVIDIA Kernel.

See “Building the NVIDIA Kernel” https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fkernel_custom.html%23wwpID0E0FD0HA

Note: The sample root file system was integrated into the L4T rootfs folder prior to transferring kernel output files to L4T and installing the kernel.

8. Apply binaries.

$ sudo ./apply_binaries.sh

This was initially performed on an Ubuntu 16.04 host computer, which resulted in errors. Running on Ubuntu 18.04 resulted in “Success!”

9. Connect to Xavier USB-C port on back side (where the GPIO pins live).

10. Flash kernel.

$ sudo ./flash.sh -k kernel-dtb jetson-xavier mmcblk0p1

Incoporating the -r switch in the ./flash.sh command failed because it looks for system.img, which was not built.


I understand that my driver could be so far out of tune that it wouldn’t pick up a single valid video frame from the FPGA. That will require adjusting, and possibly an additional post to the forums. However, I do not understand what needs to be corrected to identify /dev/video0.

Any help or feedback would be greatly apprecited.

Thanks!
Ian

So you have problem to gen the video0?
I would suggest to using the ov5693 as template and remove all i2c code for it.

Hi @ShaneCCC ,

Thank you for responding on the same day of my original post. I’ve made some progress, but still unable to capture from the FPGA.

Here’s the good news: /dev/video0 now appears. The following dmesg output just shows its binding.

$nvidia@xavier:~$ dmesg
...
[    7.108554] ov5693 2-0036: probing v4l2 sensor no i2c.
[    7.109445] ov5693 2-0036: tegracam sensor driver:ov5693_v2.0.6
[    7.109486] tegra194-vi5 15c10000.vi: subdev ov5693 2-0036 bound
...

The bad news: The Xavier is unable to capture frames. After /dev/video0 appeared successfully, I’ve tried various edits of tegra194-camera-e3326-a00.dtsi to match the MIPI signal specs coming in from the FPGA, but the capture results have all been the same.

The following shows that the driver and device tree changes successfully applied after flashing.

nvidia@xavier:~$ v4l2-ctl --list-formats-ext
ioctl: VIDIOC_ENUM_FMT
	Index       : 0
	Type        : Video Capture
	Pixel Format: 'YUYV'
	Name        : YUYV 4:2:2
		Size: Discrete 1920x1080
			Interval: Discrete 0.033s (30.000 fps)

	Index       : 1
	Type        : Video Capture
	Pixel Format: 'YUYV'
	Name        : YUYV 4:2:2
		Size: Discrete 1920x1080
			Interval: Discrete 0.033s (30.000 fps)

Displaying more information indicates “Camera 2: no power.” I’m not sure if this is important since the device is an FPGA, and not a camera.

nvidia@xavier:~$ v4l2-ctl --all
Driver Info (not using libv4l2):
	Driver name   : tegra-video
	Card type     : vi-output, ov5693 2-0036
	Bus info      : platform:15c10000.vi:2
	Driver version: 4.9.140
	Capabilities  : 0x84200001
		Video Capture
		Streaming
		Extended Pix Format
		Device Capabilities
	Device Caps   : 0x04200001
		Video Capture
		Streaming
		Extended Pix Format
Priority: 2
Video input : 0 (Camera 2: no power)
Format Video Capture:
	Width/Height      : 1920/1080
	Pixel Format      : 'YUYV'
	Field             : None
	Bytes per Line    : 3840
	Size Image        : 4147200
	Colorspace        : sRGB
	Transfer Function : Default (maps to sRGB)
	YCbCr/HSV Encoding: Default (maps to ITU-R 601)
	Quantization      : Default (maps to Limited Range)
	Flags             : 

Camera Controls

                     group_hold 0x009a2003 (bool)   : default=0 value=0 flags=execute-on-write
                     hdr_enable 0x009a2004 (intmenu): min=0 max=1 default=0 value=0
                           gain 0x009a2009 (int64)  : min=0 max=0 step=0 default=0 value=10 flags=slider
                       exposure 0x009a200a (int64)  : min=0 max=0 step=0 default=0 value=34 flags=slider
                     frame_rate 0x009a200b (int64)  : min=0 max=0 step=0 default=0 value=1816577 flags=slider
                 exposure_short 0x009a200c (int64)  : min=0 max=0 step=0 default=0 value=34 flags=slider
           sensor_configuration 0x009a2032 (u32)    : min=0 max=0 step=0 default=0 flags=read-only, volatile, has-payload
         sensor_mode_i2c_packet 0x009a2033 (u32)    : min=0 max=0 step=0 default=0 flags=read-only, volatile, has-payload
      sensor_control_i2c_packet 0x009a2034 (u32)    : min=0 max=0 step=0 default=0 flags=read-only, volatile, has-payload
                    bypass_mode 0x009a2064 (intmenu): min=0 max=1 default=0 value=0
                override_enable 0x009a2065 (intmenu): min=0 max=1 default=0 value=0
                   height_align 0x009a2066 (int)    : min=1 max=16 step=1 default=1 value=1
                     size_align 0x009a2067 (intmenu): min=0 max=2 default=0 value=0
               write_isp_format 0x009a2068 (int)    : min=1 max=1 step=1 default=1 value=1
       sensor_signal_properties 0x009a2069 (u32)    : min=0 max=0 step=0 default=0 flags=read-only, has-payload
        sensor_image_properties 0x009a206a (u32)    : min=0 max=0 step=0 default=0 flags=read-only, has-payload
      sensor_control_properties 0x009a206b (u32)    : min=0 max=0 step=0 default=0 flags=read-only, has-payload
              sensor_dv_timings 0x009a206c (u32)    : min=0 max=0 step=0 default=0 flags=read-only, has-payload
               low_latency_mode 0x009a206d (bool)   : default=0 value=0
               preferred_stride 0x009a206e (int)    : min=0 max=65535 step=1 default=0 value=0
                   sensor_modes 0x009a2082 (int)    : min=0 max=30 step=1 default=30 value=1 flags=read-only

v4l2-compliance results in 2 failures.

nvidia@xavier:~$ v4l2-compliance
v4l2-compliance SHA   : not available

Driver Info:
	Driver name   : tegra-video
	Card type     : vi-output, ov5693 2-0036
	Bus info      : platform:15c10000.vi:2
	Driver version: 4.9.140
	Capabilities  : 0x84200001
		Video Capture
		Streaming
		Extended Pix Format
		Device Capabilities
	Device Caps   : 0x04200001
		Video Capture
		Streaming
		Extended Pix Format

Compliance test for device /dev/video0 (not using libv4l2):

Required ioctls:
	test VIDIOC_QUERYCAP: OK

Allow for multiple opens:
	test second video open: OK
	test VIDIOC_QUERYCAP: OK
	test VIDIOC_G/S_PRIORITY: OK
	test for unlimited opens: OK

Debug ioctls:
	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
	test VIDIOC_LOG_STATUS: OK

Input ioctls:
	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
	test VIDIOC_ENUMAUDIO: OK (Not Supported)
	test VIDIOC_G/S/ENUMINPUT: OK
	test VIDIOC_G/S_AUDIO: OK (Not Supported)
	Inputs: 1 Audio Inputs: 0 Tuners: 0

Output ioctls:
	test VIDIOC_G/S_MODULATOR: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_ENUMAUDOUT: OK (Not Supported)
	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
	test VIDIOC_G/S_AUDOUT: OK (Not Supported)
	Outputs: 0 Audio Outputs: 0 Modulators: 0

Input/Output configuration ioctls:
	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
	test VIDIOC_G/S_EDID: OK (Not Supported)

Test input 0:

	Control ioctls:
		test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
		test VIDIOC_QUERYCTRL: OK
		test VIDIOC_G/S_CTRL: OK
		test VIDIOC_G/S/TRY_EXT_CTRLS: OK
		test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
		test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
		Standard Controls: 1 Private Controls: 21

	Format ioctls:
		fail: v4l2-test-formats.cpp(273): duplicate format 56595559 (YUYV)
		test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: FAIL
		fail: v4l2-test-formats.cpp(1184): ret && node->has_frmintervals
		test VIDIOC_G/S_PARM: FAIL
		test VIDIOC_G_FBUF: OK (Not Supported)
		test VIDIOC_G_FMT: OK
		test VIDIOC_TRY_FMT: OK
		test VIDIOC_S_FMT: OK
		test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
		test Cropping: OK (Not Supported)
		test Composing: OK (Not Supported)
		test Scaling: OK (Not Supported)

	Codec ioctls:
		test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
		test VIDIOC_G_ENC_INDEX: OK (Not Supported)
		test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)

	Buffer ioctls:
		test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
		test VIDIOC_EXPBUF: OK

Test input 0:


Total: 43, Succeeded: 41, Failed: 2, Warnings: 0

Attempting to capture video results in “mapped, error” flags.

nvidia@xavier:~$ v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 --stream-to=test.raw --verbose
VIDIOC_QUERYCAP: ok
VIDIOC_S_EXT_CTRLS: ok
VIDIOC_REQBUFS: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_STREAMON: ok
	Index    : 0
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 0
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 0
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 0
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 1
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 1
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 2
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 2
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 3
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 3
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

Output from dmesg while attempting to capture shows the following “no callback” and “no reply” messages, along with [RCE] messages. The “no reply” and [RCE] messages repeat as long as the v4l-ctl command for capture is active.

nvidia@xavier:~$ dmesg --follow
...
[  646.329062] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
[  649.049066] tegra194-vi5 15c10000.vi: no reply from camera processor
[  649.049238] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  649.049421] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  649.051956] tegra-capture-ivc ivc-bc00000.rtcpu:ivccontrol@3: No callback found for msg id: 0x39
[  649.052198] tegra-capture-ivc ivc-bc00000.rtcpu:ivccontrol@3: No callback found for msg id: 0x41
[  649.052355] tegra-capture-ivc ivc-bc00000.rtcpu:ivccontrol@3: No callback found for msg id: 0x37
[  649.052569] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  651.609039] tegra194-vi5 15c10000.vi: no reply from camera processor
[  651.609234] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  651.609385] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  651.611768] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  654.169155] tegra194-vi5 15c10000.vi: no reply from camera processor
[  654.169320] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  654.169503] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  654.171807] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  656.673063] tegra194-vi5 15c10000.vi: no reply from camera processor
[  656.673233] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  656.673369] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  656.675863] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
...
[  822.113081] [RCE] Configuring VI GoS.
[  822.113092] [RCE] VM GOS[#0] addr=0xc2100000
[  822.113123] [RCE] VM GOS[#1] addr=0xc2101000
[  822.113127] [RCE] VM GOS[#2] addr=0xc2102000
[  822.113132] [RCE] VM GOS[#3] addr=0xc2103000
[  822.113137] [RCE] VM GOS[#4] addr=0xc2104000
[  822.113142] [RCE] VM GOS[#5] addr=0xc2105000
[  822.113148] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
[  822.113156] [RCE] VI GOS[#0] set to VM GOS[4] base 0xc2104000
[  824.665113] tegra194-vi5 15c10000.vi: no reply from camera processor
[  824.665285] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  824.665437] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  824.668518] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel

Results of boosting the clock appear normal, but the capture results do not change.

root@xavier:/home/nvidia# echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
root@xavier:/home/nvidia# echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
root@xavier:/home/nvidia# echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
root@xavier:/home/nvidia# cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
998400000
root@xavier:/home/nvidia# cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee  /sys/kernel/debug/bpmp/debug/clk/isp/rate
1190400000
root@xavier:/home/nvidia# cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
400000000

Running a trace produces a series of failures:

root@xavier:/home/nvidia# echo 1 > /sys/kernel/debug/tracing/tracing_on
root@xavier:/home/nvidia# echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
root@xavier:/home/nvidia# echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
root@xavier:/home/nvidia# echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
root@xavier:/home/nvidia# echo 2 > /sys/kernel/debug/camrtc/log-level
root@xavier:/home/nvidia# echo 1 > /sys/kernel/debug/tracing/events/camera_common/enable
root@xavier:/home/nvidia# echo > /sys/kernel/debug/tracing/trace
root@xavier:/home/nvidia# cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 55/55   #P:4
#
#                              _-----=> irqs-off
#                             / _----=> need-resched
#                            | / _---=> hardirq/softirq
#                            || / _--=> preempt-depth
#                            ||| /     delay
#           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
#              | |       |   ||||       |         |
     kworker/0:2-8798  [000] ....   834.781128: rtos_queue_peek_from_isr_failed: tstamp:26455774612 queue:0x0bcbcf78
 vi-output, ov56-9418  [000] ....   834.907538: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 10
     kworker/0:2-8798  [000] ....   834.949053: rtos_queue_send_from_isr_failed: tstamp:26460695653 queue:0x0bcb41f8
     kworker/0:2-8798  [000] ....   834.949059: rtos_queue_send_from_isr_failed: tstamp:26460695815 queue:0x0bcb8a60
     kworker/0:2-8798  [000] ....   834.949061: rtos_queue_send_from_isr_failed: tstamp:26460695976 queue:0x0bcba5e0
     kworker/0:2-8798  [000] ....   834.949062: rtos_queue_send_from_isr_failed: tstamp:26460696138 queue:0x0bcbb3a0
     kworker/0:2-8798  [000] ....   834.949063: rtos_queue_send_from_isr_failed: tstamp:26460696295 queue:0x0bcbc160
     kworker/0:2-8798  [000] ....   834.949065: rtos_queue_send_from_isr_failed: tstamp:26460754717 queue:0x0bcb41f8
     kworker/0:2-8798  [000] ....   834.949066: rtos_queue_send_from_isr_failed: tstamp:26460754877 queue:0x0bcb8a60
     kworker/0:2-8798  [000] ....   834.949068: rtos_queue_send_from_isr_failed: tstamp:26460755039 queue:0x0bcba5e0
     kworker/0:2-8798  [000] ....   834.949069: rtos_queue_send_from_isr_failed: tstamp:26460755197 queue:0x0bcbb3a0
     kworker/0:2-8798  [000] ....   834.949070: rtos_queue_send_from_isr_failed: tstamp:26460755352 queue:0x0bcbc160
     kworker/0:2-8798  [000] ....   834.949074: rtcpu_string: tstamp:26460761763 id:0x04010000 str:"Configuring VI GoS.
"
     kworker/0:2-8798  [000] ....   834.949120: rtcpu_string: tstamp:26460761972 id:0x04010000 str:"VM GOS[#0] addr=0xc2100000
"
     kworker/0:2-8798  [000] ....   834.949127: rtcpu_string: tstamp:26460762235 id:0x04010000 str:"VM GOS[#1] addr=0xc2101000
"
     kworker/0:2-8798  [000] ....   834.949134: rtcpu_string: tstamp:26460762513 id:0x04010000 str:"VM GOS[#2] addr=0xc2102000
"
     kworker/0:2-8798  [000] ....   834.949141: rtcpu_string: tstamp:26460762755 id:0x04010000 str:"VM GOS[#3] addr=0xc2103000
"
     kworker/0:2-8798  [000] ....   834.949147: rtcpu_string: tstamp:26460762998 id:0x04010000 str:"VM GOS[#4] addr=0xc2104000
"
     kworker/0:2-8798  [000] ....   834.949153: rtcpu_string: tstamp:26460763240 id:0x04010000 str:"VM GOS[#5] addr=0xc2105000
"
     kworker/0:2-8798  [000] ....   834.949190: rtos_queue_send_from_isr_failed: tstamp:26460767921 queue:0x0bcb41f8
     kworker/0:2-8798  [000] ....   834.949191: rtos_queue_send_from_isr_failed: tstamp:26460768081 queue:0x0bcb8a60
     kworker/0:2-8798  [000] ....   834.949193: rtos_queue_send_from_isr_failed: tstamp:26460768243 queue:0x0bcba5e0
     kworker/0:2-8798  [000] ....   834.949194: rtos_queue_send_from_isr_failed: tstamp:26460768398 queue:0x0bcbb3a0
     kworker/0:2-8798  [000] ....   834.949195: rtos_queue_send_from_isr_failed: tstamp:26460768554 queue:0x0bcbc160
     kworker/0:2-8798  [000] ....   834.949198: rtos_queue_peek_from_isr_failed: tstamp:26460774608 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   834.949199: rtos_queue_send_from_isr_failed: tstamp:26460779228 queue:0x0bcb41f8
     kworker/0:2-8798  [000] ....   834.949201: rtos_queue_send_from_isr_failed: tstamp:26460779389 queue:0x0bcb8a60
     kworker/0:2-8798  [000] ....   834.949202: rtos_queue_send_from_isr_failed: tstamp:26460779550 queue:0x0bcba5e0
     kworker/0:2-8798  [000] ....   834.949203: rtos_queue_send_from_isr_failed: tstamp:26460779705 queue:0x0bcbb3a0
     kworker/0:2-8798  [000] ....   834.949205: rtos_queue_send_from_isr_failed: tstamp:26460779861 queue:0x0bcbc160
     kworker/0:2-8798  [000] ....   834.949206: rtos_queue_send_from_isr_failed: tstamp:26460788485 queue:0x0bcb41f8
     kworker/0:2-8798  [000] ....   834.949208: rtos_queue_send_from_isr_failed: tstamp:26460788643 queue:0x0bcb8a60
     kworker/0:2-8798  [000] ....   834.949209: rtos_queue_send_from_isr_failed: tstamp:26460788804 queue:0x0bcba5e0
     kworker/0:2-8798  [000] ....   834.949210: rtos_queue_send_from_isr_failed: tstamp:26460788965 queue:0x0bcbb3a0
     kworker/0:2-8798  [000] ....   834.949212: rtos_queue_send_from_isr_failed: tstamp:26460789119 queue:0x0bcbc160
     kworker/0:2-8798  [000] ....   834.949213: rtos_queue_send_from_isr_failed: tstamp:26460799931 queue:0x0bcb41f8
     kworker/0:2-8798  [000] ....   834.949214: rtos_queue_send_from_isr_failed: tstamp:26460800089 queue:0x0bcb8a60
     kworker/0:2-8798  [000] ....   834.949216: rtos_queue_send_from_isr_failed: tstamp:26460800250 queue:0x0bcba5e0
     kworker/0:2-8798  [000] ....   834.949217: rtos_queue_send_from_isr_failed: tstamp:26460800406 queue:0x0bcbb3a0
     kworker/0:2-8798  [000] ....   834.949218: rtos_queue_send_from_isr_failed: tstamp:26460800562 queue:0x0bcbc160
     kworker/0:2-8798  [000] ....   834.949221: rtcpu_vinotify_event: tstamp:26461038493 tag:RESERVED_18 channel:0x23 frame:0 vi_tstamp:26405888704 data:0x10000000
     kworker/0:2-8798  [000] ....   834.949223: rtcpu_vinotify_event: tstamp:26461038674 tag:RESERVED_18 channel:0x23 frame:0 vi_tstamp:26405892512 data:0x31000001
     kworker/0:2-8798  [000] ....   834.949224: rtcpu_vinotify_event: tstamp:26461038826 tag:RESERVED_19 channel:0x23 frame:0 vi_tstamp:26405893504 data:0x07020001
     kworker/0:2-8798  [000] ....   834.949226: rtcpu_vinotify_event: tstamp:26461038997 tag:RESERVED_18 channel:0x23 frame:0 vi_tstamp:26406249088 data:0x10000000
     kworker/0:2-8798  [000] ....   834.949227: rtcpu_vinotify_event: tstamp:26461039144 tag:RESERVED_18 channel:0x23 frame:0 vi_tstamp:26406252960 data:0x31000002
     kworker/0:2-8798  [000] ....   835.117032: rtos_queue_peek_from_isr_failed: tstamp:26465774613 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   835.229022: rtos_queue_peek_from_isr_failed: tstamp:26470774613 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   835.397026: rtos_queue_peek_from_isr_failed: tstamp:26475774613 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   835.565041: rtos_queue_peek_from_isr_failed: tstamp:26480774606 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   835.733049: rtos_queue_peek_from_isr_failed: tstamp:26485774607 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   835.901035: rtos_queue_peek_from_isr_failed: tstamp:26490774608 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   836.069076: rtos_queue_peek_from_isr_failed: tstamp:26495774613 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   836.237037: rtos_queue_peek_from_isr_failed: tstamp:26500774612 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   836.349060: rtos_queue_peek_from_isr_failed: tstamp:26505774611 queue:0x0bcbcf78
     kworker/0:2-8798  [000] ....   836.517055: rtos_queue_peek_from_isr_failed: tstamp:26510774612 queue:0x0bcbcf78

I’m stumped here. If you have any thoughts, please let me know.

Thanks!
Ian

The trace log show NVCSI/VI didn’t receive any validate data from the MIPI bus.
You may need to probe the MIPI signal to confirm it.

Hi @ShaneCCC,

Thank you for replying so quickly again.

I have probed the MIPI signals through the Leopard Imaging board, and I know they exist. (I can provide oscilloscope screenshots if helpful.) My FPGA developer is using Xilinx IP for MIPI CSI-2 output from the FPGA, so I have gone on the assumption that the MIPI signals from the FPGA are okay since that eliminates the problems of a lot of hand-coded errors.

My questions about the MIPI signals at this point:

  1. As opposed to a straight-through connection, could the Leopard Imaging board cause any issues? I’ve noticed that it writes to addresses 0x54 and 0x70 when its plugged in.

  2. We are using 4 CSI lanes. The device tree source files have been updated to accommodate this. Could this contribute to the problem of not receiving valid data from the MIPI bus?

Thanks!
Ian

For the 1. I can’t tell it. May need to consult with Leopard.
And for the 2. you can print the configure from the NVCS/VI driver to confirm if the dts configure is correct.

Thanks again @ShaneCCC!

  1. I have not yet reached out to Leopard for support, but I’ll follow up with them if it continues to be an issue.

  2. I’ll double-check the NVCS/VI/DTS source to ensure everything is correct when I get back into the office tomorrow. I’ll probably have more questions later.

Thanks!
Ian

Hi @ShaneCCC,

Good news! We were able to get the video up and running. This required changes on both the FPGA and Jetson. The functional design used single-lane MIPI CSI.

Bad news! We need 4-lane MIPI CSI. So far, this has not worked after changing the signal from the FPGA and updating the DT (bus-width, num_lanes, num_csi_lanes). As far as I understand, no further changes are required in the DT and driver source files.

v4l2-ctl just loops forever:

nvidia@xavier:~$ v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 --stream-to=test_20210204_1.uyvy --verbose
VIDIOC_QUERYCAP: ok
VIDIOC_S_EXT_CTRLS: ok
VIDIOC_REQBUFS: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_STREAMON: ok
	Index    : 0
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 0
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 0
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 0
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 1
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 1
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 2
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 2
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

	Index    : 3
	Type     : Video Capture
	Flags    : mapped, error
	Field    : None
	Sequence : 3
	Length   : 4147200
	Bytesused: 4147200
	Timestamp: 0.000000s (Monotonic, End-of-Frame)

Trace output. The GLOBAL and CORRECTABLE_ERR messages loop forever.

root@xavier:/home/nvidia# cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 271771/271771   #P:4
#
#                              _-----=> irqs-off
#                             / _----=> need-resched
#                            | / _---=> hardirq/softirq
#                            || / _--=> preempt-depth
#                            ||| /     delay
#           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
#              | |       |   ||||       |         |
     kworker/0:3-1652  [000] ....   124.000935: rtos_queue_peek_from_isr_failed: tstamp:4222656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   124.168924: rtos_queue_peek_from_isr_failed: tstamp:4227656400 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   124.336891: rtos_queue_peek_from_isr_failed: tstamp:4232656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   124.504875: rtos_queue_peek_from_isr_failed: tstamp:4237656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   124.672908: rtos_queue_peek_from_isr_failed: tstamp:4242656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   124.784878: rtos_queue_peek_from_isr_failed: tstamp:4247656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   124.952918: rtos_queue_peek_from_isr_failed: tstamp:4252656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   125.120910: rtos_queue_peek_from_isr_failed: tstamp:4257656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   125.288939: rtos_queue_peek_from_isr_failed: tstamp:4262656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   125.456952: rtos_queue_peek_from_isr_failed: tstamp:4267656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   125.624974: rtos_queue_peek_from_isr_failed: tstamp:4272656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   125.792907: rtos_queue_peek_from_isr_failed: tstamp:4277656403 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   125.904913: rtos_queue_peek_from_isr_failed: tstamp:4282656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   126.072959: rtos_queue_peek_from_isr_failed: tstamp:4287656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   126.240983: rtos_queue_peek_from_isr_failed: tstamp:4292656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   126.408935: rtos_queue_peek_from_isr_failed: tstamp:4297656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   126.576916: rtos_queue_peek_from_isr_failed: tstamp:4302656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   126.744936: rtos_queue_peek_from_isr_failed: tstamp:4307656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   126.912933: rtos_queue_peek_from_isr_failed: tstamp:4312656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   127.024933: rtos_queue_peek_from_isr_failed: tstamp:4317656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   127.192933: rtos_queue_peek_from_isr_failed: tstamp:4322656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   127.360917: rtos_queue_peek_from_isr_failed: tstamp:4327656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   127.528943: rtos_queue_peek_from_isr_failed: tstamp:4332656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   127.696915: rtos_queue_peek_from_isr_failed: tstamp:4337656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   127.864936: rtos_queue_peek_from_isr_failed: tstamp:4342656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   128.032945: rtos_queue_peek_from_isr_failed: tstamp:4347656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   128.144942: rtos_queue_peek_from_isr_failed: tstamp:4352656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   128.312921: rtos_queue_peek_from_isr_failed: tstamp:4357656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   128.480891: rtos_queue_peek_from_isr_failed: tstamp:4362656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   128.648906: rtos_queue_peek_from_isr_failed: tstamp:4367656397 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   128.816900: rtos_queue_peek_from_isr_failed: tstamp:4372656404 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   128.984887: rtos_queue_peek_from_isr_failed: tstamp:4377656398 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   129.152883: rtos_queue_peek_from_isr_failed: tstamp:4382656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   129.264885: rtos_queue_peek_from_isr_failed: tstamp:4387656399 queue:0x0bcbcf78
     kworker/0:3-1652  [000] ....   129.376903: rtos_queue_peek_from_isr_failed: tstamp:4391245765 queue:0x0bcbcf78
        v4l2-ctl-8625  [003] ....   146.728575: tegra_channel_open: vi-output, ov5693 30-001a
        v4l2-ctl-8625  [002] ....   146.731453: tegra_channel_set_power: ov5693 30-001a : 0x1
        v4l2-ctl-8625  [002] ....   146.731469: camera_common_s_power: status : 0x1
        v4l2-ctl-8625  [002] ....   146.736243: tegra_channel_set_power: 15a00000.nvcsi--1 : 0x1
        v4l2-ctl-8625  [002] ....   146.736248: csi_s_power: enable : 0x1
        v4l2-ctl-8625  [000] ....   146.743514: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 13
        v4l2-ctl-8625  [000] ....   146.747018: tegra_channel_set_stream: enable : 0x1
        v4l2-ctl-8625  [000] ....   146.748672: tegra_channel_set_stream: 15a00000.nvcsi--1 : 0x1
        v4l2-ctl-8625  [000] ....   146.748677: csi_s_stream: enable : 0x1
        v4l2-ctl-8625  [000] ....   146.748705: tegra_channel_set_stream: ov5693 30-001a : 0x1
     kworker/0:0-4     [000] ....   146.796890: rtos_queue_peek_from_isr_failed: tstamp:4934144483 queue:0x0bcbcf78
     kworker/0:0-4     [000] ....   146.796897: rtcpu_start: tstamp:4934146364
     kworker/0:0-4     [000] ....   146.796898: rtos_queue_send_from_isr_failed: tstamp:4934156312 queue:0x0bcb41f8
     kworker/0:0-4     [000] ....   146.796899: rtos_queue_send_from_isr_failed: tstamp:4934156474 queue:0x0bcb8a60
     kworker/0:0-4     [000] ....   146.796900: rtos_queue_send_from_isr_failed: tstamp:4934156635 queue:0x0bcba5e0
     kworker/0:0-4     [000] ....   146.796901: rtos_queue_send_from_isr_failed: tstamp:4934156792 queue:0x0bcbb3a0
     kworker/0:0-4     [000] ....   146.796901: rtos_queue_send_from_isr_failed: tstamp:4934156949 queue:0x0bcbc160
     kworker/0:0-4     [000] ....   146.796903: rtcpu_string: tstamp:4934157400 id:0x04010000 str:"Configuring VI GoS.
"
     kworker/0:0-4     [000] ....   146.796931: rtcpu_string: tstamp:4934157593 id:0x04010000 str:"VM GOS[#0] addr=0xc2100000
"
     kworker/0:0-4     [000] ....   146.796944: rtcpu_string: tstamp:4934157862 id:0x04010000 str:"VM GOS[#1] addr=0xc2101000
"
     kworker/0:0-4     [000] ....   146.796951: rtcpu_string: tstamp:4934158142 id:0x04010000 str:"VM GOS[#2] addr=0xc2102000
"
     kworker/0:0-4     [000] ....   146.796957: rtcpu_string: tstamp:4934158383 id:0x04010000 str:"VM GOS[#3] addr=0xc2103000
"
     kworker/0:0-4     [000] ....   146.796963: rtcpu_string: tstamp:4934158624 id:0x04010000 str:"VM GOS[#4] addr=0xc2104000
"
     kworker/0:0-4     [000] ....   146.796969: rtcpu_string: tstamp:4934158867 id:0x04010000 str:"VM GOS[#5] addr=0xc2105000
"
     kworker/0:0-4     [000] ....   146.796975: rtcpu_string: tstamp:4934166463 id:0x04010000 str:"vi5_hwinit: firmware CL2018101701 protocol versi"
     kworker/0:0-4     [000] ....   146.796977: rtcpu_string: tstamp:4934166592 id:0x04010000 str:"on 2.2
"
     kworker/0:0-4     [000] ....   146.796983: rtos_queue_send_from_isr_failed: tstamp:4934183418 queue:0x0bcb41f8
     kworker/0:0-4     [000] ....   146.796984: rtos_queue_send_from_isr_failed: tstamp:4934183600 queue:0x0bcb8a60
     kworker/0:0-4     [000] ....   146.796984: rtos_queue_send_from_isr_failed: tstamp:4934183764 queue:0x0bcba5e0
     kworker/0:0-4     [000] ....   146.796985: rtos_queue_send_from_isr_failed: tstamp:4934183923 queue:0x0bcbb3a0
     kworker/0:0-4     [000] ....   146.796986: rtos_queue_send_from_isr_failed: tstamp:4934184078 queue:0x0bcbc160
     kworker/0:0-4     [000] ....   146.796986: rtcpu_string: tstamp:4934185000 id:0x04010000 str:"VI GOS[#0] set to VM GOS[4] base 0xc2104000
"
     kworker/0:0-4     [000] ....   146.796992: rtos_queue_send_from_isr_failed: tstamp:4934236638 queue:0x0bcb41f8
     kworker/0:0-4     [000] ....   146.796993: rtos_queue_send_from_isr_failed: tstamp:4934236801 queue:0x0bcb8a60
     kworker/0:0-4     [000] ....   146.796994: rtos_queue_send_from_isr_failed: tstamp:4934236967 queue:0x0bcba5e0
     kworker/0:0-4     [000] ....   146.796994: rtos_queue_send_from_isr_failed: tstamp:4934237123 queue:0x0bcbb3a0
     kworker/0:0-4     [000] ....   146.796995: rtos_queue_send_from_isr_failed: tstamp:4934237281 queue:0x0bcbc160
     kworker/0:0-4     [000] ....   146.796997: rtcpu_nvcsi_intr: tstamp:4934239865 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000001
     kworker/0:0-4     [000] ....   146.796997: rtcpu_nvcsi_intr: tstamp:4934242998 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.796998: rtcpu_nvcsi_intr: tstamp:4934242998 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.796999: rtcpu_nvcsi_intr: tstamp:4934243579 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797000: rtcpu_nvcsi_intr: tstamp:4934243579 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797000: rtcpu_nvcsi_intr: tstamp:4934244151 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797030: rtcpu_nvcsi_intr: tstamp:4934244151 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797031: rtcpu_nvcsi_intr: tstamp:4934244721 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797031: rtcpu_nvcsi_intr: tstamp:4934244721 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797032: rtcpu_nvcsi_intr: tstamp:4934245293 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797033: rtcpu_nvcsi_intr: tstamp:4934245293 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797034: rtcpu_nvcsi_intr: tstamp:4934245865 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797034: rtcpu_nvcsi_intr: tstamp:4934245865 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797035: rtcpu_nvcsi_intr: tstamp:4934246428 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797036: rtcpu_nvcsi_intr: tstamp:4934246428 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797036: rtcpu_nvcsi_intr: tstamp:4934246994 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797037: rtcpu_nvcsi_intr: tstamp:4934246994 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797038: rtcpu_nvcsi_intr: tstamp:4934247566 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797038: rtcpu_nvcsi_intr: tstamp:4934247566 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797039: rtcpu_nvcsi_intr: tstamp:4934248137 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] .n..   146.797040: rtcpu_nvcsi_intr: tstamp:4934248137 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797088: rtcpu_nvcsi_intr: tstamp:4934248707 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797089: rtcpu_nvcsi_intr: tstamp:4934248707 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797090: rtcpu_nvcsi_intr: tstamp:4934249274 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797090: rtcpu_nvcsi_intr: tstamp:4934249274 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797091: rtcpu_nvcsi_intr: tstamp:4934249843 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797092: rtcpu_nvcsi_intr: tstamp:4934249843 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797092: rtcpu_nvcsi_intr: tstamp:4934250407 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797093: rtcpu_nvcsi_intr: tstamp:4934250407 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797094: rtcpu_nvcsi_intr: tstamp:4934250975 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797095: rtcpu_nvcsi_intr: tstamp:4934250975 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797095: rtcpu_nvcsi_intr: tstamp:4934251552 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797096: rtcpu_nvcsi_intr: tstamp:4934251552 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797097: rtcpu_nvcsi_intr: tstamp:4934252120 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797097: rtcpu_nvcsi_intr: tstamp:4934252120 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797098: rtcpu_nvcsi_intr: tstamp:4934252684 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040
     kworker/0:0-4     [000] ....   146.797099: rtcpu_nvcsi_intr: tstamp:4934252684 class:CORRECTABLE_ERR type:PHY_INTR phy:0 cil:0 st:0 vc:0 status:0x00001040
     kworker/0:0-4     [000] ....   146.797099: rtcpu_nvcsi_intr: tstamp:4934253252 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040

Kernel output:

nvidia@xavier:~$ dmesg
. . .
[  146.747877] misc tegra_camera_ctrl: tegra_camera_update_isobw: Warning, Requested ISO BW 4882812 has been capped to VI's max BW 1875000
[  146.796925] [RCE] Configuring VI GoS.
[  146.796942] [RCE] VM GOS[#0] addr=0xc2100000
[  146.796949] [RCE] VM GOS[#1] addr=0xc2101000
[  146.796955] [RCE] VM GOS[#2] addr=0xc2102000
[  146.796961] [RCE] VM GOS[#3] addr=0xc2103000
[  146.796967] [RCE] VM GOS[#4] addr=0xc2104000
[  146.796973] [RCE] VM GOS[#5] addr=0xc2105000
[  146.796980] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
[  146.796990] [RCE] VI GOS[#0] set to VM GOS[4] base 0xc2104000
[  149.340913] tegra194-vi5 15c10000.vi: no reply from camera processor
[  149.341114] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  149.341264] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  149.343983] tegra-capture-ivc ivc-bc00000.rtcpu:ivccontrol@3: No callback found for msg id: 0x39
[  149.344185] tegra-capture-ivc ivc-bc00000.rtcpu:ivccontrol@3: No callback found for msg id: 0x41
[  149.344341] tegra-capture-ivc ivc-bc00000.rtcpu:ivccontrol@3: No callback found for msg id: 0x37
[  149.344531] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  149.373209] [RCE] Configuring VI GoS.
[  149.373230] [RCE] VM GOS[#0] addr=0xc2100000
[  149.373248] [RCE] VM GOS[#1] addr=0xc2101000
[  149.373262] [RCE] VM GOS[#2] addr=0xc2102000
[  149.373276] [RCE] VM GOS[#3] addr=0xc2103000
[  149.373289] [RCE] VM GOS[#4] addr=0xc2104000
[  149.373302] [RCE] VM GOS[#5] addr=0xc2105000
[  151.900896] tegra194-vi5 15c10000.vi: no reply from camera processor
[  151.901070] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  151.901218] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  151.904147] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  151.948907] [RCE] Configuring VI GoS.
[  151.948924] [RCE] VM GOS[#0] addr=0xc2100000
[  151.948949] [RCE] VM GOS[#1] addr=0xc2101000
[  151.948960] [RCE] VM GOS[#2] addr=0xc2102000
[  151.948973] [RCE] VM GOS[#3] addr=0xc2103000
[  151.948983] [RCE] VM GOS[#4] addr=0xc2104000
[  151.948986] [RCE] VM GOS[#5] addr=0xc2105000
 . . .
[  479.324948] tegra194-vi5 15c10000.vi: no reply from camera processor
[  479.325128] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  479.325286] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  479.343488] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  479.369562] [RCE] Configuring VI GoS.
[  479.369583] [RCE] VM GOS[#0] addr=0xc2100000
[  479.369630] [RCE] VM GOS[#1] addr=0xc2101000
[  479.369678] [RCE] VM GOS[#2] addr=0xc2102000
[  479.369692] [RCE] VM GOS[#3] addr=0xc2103000
[  479.369704] [RCE] VM GOS[#4] addr=0xc2104000
[  479.369717] [RCE] VM GOS[#5] addr=0xc2105000
[  481.884892] tegra194-vi5 15c10000.vi: no reply from camera processor
[  481.885094] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  481.885272] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  481.888197] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  481.889601] [RCE] Configuring VI GoS.
[  481.889660] [RCE] VM GOS[#0] addr=0xc2100000
[  481.889668] [RCE] VM GOS[#1] addr=0xc2101000
[  481.889674] [RCE] VM GOS[#2] addr=0xc2102000
[  481.889683] [RCE] VM GOS[#3] addr=0xc2103000
[  481.889740] [RCE] VM GOS[#4] addr=0xc2104000
[  481.889746] [RCE] VM GOS[#5] addr=0xc2105000
[  484.444907] tegra194-vi5 15c10000.vi: no reply from camera processor
[  484.445084] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  484.445252] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  484.451165] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  484.465232] [RCE] Configuring VI GoS.
[  484.465242] [RCE] VM GOS[#0] addr=0xc2100000
[  484.465246] [RCE] VM GOS[#1] addr=0xc2101000
[  484.465249] [RCE] VM GOS[#2] addr=0xc2102000
[  484.465253] [RCE] VM GOS[#3] addr=0xc2103000
[  484.465257] [RCE] VM GOS[#4] addr=0xc2104000
[  484.465265] [RCE] VM GOS[#5] addr=0xc2105000
[  487.004898] tegra194-vi5 15c10000.vi: no reply from camera processor
[  487.005106] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  487.005258] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  487.012300] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  487.045269] [RCE] Configuring VI GoS.
[  487.045281] [RCE] VM GOS[#0] addr=0xc2100000
[  487.045285] [RCE] VM GOS[#1] addr=0xc2101000
[  487.045289] [RCE] VM GOS[#2] addr=0xc2102000
[  487.045294] [RCE] VM GOS[#3] addr=0xc2103000
[  487.045322] [RCE] VM GOS[#4] addr=0xc2104000
[  487.045327] [RCE] VM GOS[#5] addr=0xc2105000
[  489.564939] tegra194-vi5 15c10000.vi: no reply from camera processor
[  489.565160] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  489.565323] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  489.578145] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  489.621178] [RCE] Configuring VI GoS.
[  489.621193] [RCE] VM GOS[#0] addr=0xc2100000
[  489.621200] [RCE] VM GOS[#1] addr=0xc2101000
[  489.621207] [RCE] VM GOS[#2] addr=0xc2102000
[  489.621213] [RCE] VM GOS[#3] addr=0xc2103000
[  489.621219] [RCE] VM GOS[#4] addr=0xc2104000
[  489.621226] [RCE] VM GOS[#5] addr=0xc2105000
[  492.124894] tegra194-vi5 15c10000.vi: no reply from camera processor
[  492.125082] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  492.125265] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  492.142810] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  492.196922] [RCE] Configuring VI GoS.
[  492.196932] [RCE] VM GOS[#0] addr=0xc2100000
[  492.196936] [RCE] VM GOS[#1] addr=0xc2101000
[  492.196940] [RCE] VM GOS[#2] addr=0xc2102000
[  492.196970] [RCE] VM GOS[#3] addr=0xc2103000
[  492.196973] [RCE] VM GOS[#4] addr=0xc2104000
[  492.196977] [RCE] VM GOS[#5] addr=0xc2105000
[  494.684876] tegra194-vi5 15c10000.vi: no reply from camera processor
[  494.685053] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  494.685238] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  494.689077] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  494.717100] [RCE] Configuring VI GoS.
[  494.717111] [RCE] VM GOS[#0] addr=0xc2100000
[  494.717115] [RCE] VM GOS[#1] addr=0xc2101000
[  494.717118] [RCE] VM GOS[#2] addr=0xc2102000
[  494.717121] [RCE] VM GOS[#3] addr=0xc2103000
[  494.717125] [RCE] VM GOS[#4] addr=0xc2104000
[  494.717128] [RCE] VM GOS[#5] addr=0xc2105000
[  497.244892] tegra194-vi5 15c10000.vi: no reply from camera processor
[  497.245096] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[  497.245269] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[  497.248025] tegra194-vi5 15c10000.vi: err_rec: successfully reset the capture channel
[  497.292979] [RCE] Configuring VI GoS.
[  497.292989] [RCE] VM GOS[#0] addr=0xc2100000
[  497.292993] [RCE] VM GOS[#1] addr=0xc2101000
[  497.292997] [RCE] VM GOS[#2] addr=0xc2102000
[  497.293000] [RCE] VM GOS[#3] addr=0xc2103000
[  497.293003] [RCE] VM GOS[#4] addr=0xc2104000
[  497.293006] [RCE] VM GOS[#5] addr=0xc2105000

Looking at the messages in the trace, perhaps this is related to NVCSI_PHY_0_CILA_INTR_0_STATUS_CILA_0, specifically intr_cil_data_lane_sot_mb_err1_a, but I’m not certain. Your insight would be greatly appreciated here.

Thanks!
Ian

Yes, this trace message tell the REG NVCSI_PHY_0_CILA_INTR_0_STATUS_CILA_0 status

kworker/0:0-4 [000] … 146.796999: rtcpu_nvcsi_intr: tstamp:4934243579 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x10000040

Thanks @ShaneCCC!

Can you share any more information on what this means exactly? (i.e., What is wrong with the signal? How to fix?)

Thanks!
Ian

It’s tell start of transmission for multiple bit error. That could be the output signal problem.

Super helpful. I’ll see what we can do about it tomorrow in the office. Thanks again, @ShaneCCC!

Hi @ShaneCCC,

I just wanted to follow up. Turns out we had some faulty FMC pins on the FPGA board. Swapping out the FPGA board entirely fixed the issue. Now we’re up and running with 4-lane signals. Thank you for all your advice here.

Thanks!
Ian

Hello,

I have a similar condition:
use Jetson AGX Xavier MIPI CSI-2 without I2C from MIPI Image generator.

I just follow this article’s Step1 to Step10, I think it should be work, but it doesn’t…
When I use gstreamer to show stream, there has some error message in log.
gstreamer_log (9.8 KB)

So, I traced the nvarguscamera plugin’s source code, but I notice that I can only trace down till acquireFrame() function, this function is an API provided by libargus, I have some question…

1.Why do I have this error message? Is it occurred by can’t read frame end or frame start before the time threshold?
But I just follow up on this article’s Step 1 to Step 10…

2.Do libargus have public source code?
Because I can’t trace down what did it do, what’s nvarguscamerasrc plugin’s workflow…

I am confused, Could you give me any advice?

Thanks a lot!
Josh

Hi chemistry0421,

Please help to open a new topic if it’s sill an issue. Thanks

Hi @ian.draney

i use the ov5693 without i2c to create the devicenode of video0.
But i meet the problem , i put the dmesg below

root@dev-desktop:~# dmesg | grep 5693
[    1.756931] usbcore: registered new interface driver r8152
[    1.933883] ov5693 2-0036: probing v4l2 sensor no i2c.
[    1.934662] ov5693 2-0036: tegracam sensor driver:ov5693_v2.0.6
[    1.934675] ov5693 2-0036: TEGRA_CAMERA_CID_GROUP_HOLD contorl is enabled in framework by default, no need to add it in driver
[    1.934913] ov5693 2-0036: Error -22 in control ops setup
[    1.935023] ov5693 2-0036: Failed to init ctrls ov5693
[    1.935127] ov5693 2-0036: tegra camera subdev registration failed
[    1.935410] ov5693: probe of 2-0036 failed with error -22
[    7.710673] Could not create tracefs 'ov5693_s_stream' directory
[    7.710984] ov5693: module is already loaded


Did you ever meet? And what’s your solvlation ?
Thank you very much. Be glad to your answer.
z

Hi @ian.draney

I am trying to implement the same FPGA pre-configured Test Pattern Generation with the Xavier NX board. I have implemented all the steps mentioned above but I am not able to capture the CSI data.
I am facing frame discarding issues.

[  +0.005223] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 96, err_data 8388704
[  +0.002474] tegra194-vi5 15c10000.vi: corr_err: discarding frame 1, flags: 0, err_data 512
[  +0.002833] tegra194-vi5 15c10000.vi: corr_err: discarding frame 1, flags: 0, err_data 512
[  +0.008431] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 96, err_data 8388704

Could you please tell me how you resolved your issue,

Thanks,
Ajith.

Hello @ajith.kumaresh ,

This particular issue was fixed by replacing the FPGA entirely, as the original test board had faulty pins. You may want to probe the signals from the FPGA to ensure that they meet MIPI CSI-2 specifications.

As to your specific VI errors, I am unfamiliar. It may be best to start a new forum thread for your issue to get the attention of NVIDIA support developers.

Good luck!

Thanks!
Ian

Hi @ian.draney

Thanks for your reply, I got the output. The issue was on the FPGA side.

Regards,
Ajith.