Hi all,
I’d like to add some comment and add questions.
There is similar post regarding the MIPI CSI skew.
And this post ended by NVidia side answer “This skew is for PCB, in fact there is other skew in chip. The total skews are following D-PHY request.”
Let me ask the further question.
What is this “the skew for PCB”? Does this PCB mean carier board?
What does “other skew in chip” mean?
And it describes “The total skews are following D-PHY request.”
As for the specification of MIPI D-PHY, Dynamic Data to Clock Skew Window RX Tolerance is 0.5UI. The timing budget is 0.5UI in total.
So if this window is kept, is it OK (Jetson can receives MIPI CSI data) even if this trace delay skew between DQ and CLK is more than 5ps
(this means other skews are controlled small enough)?